1. Field of the Invention
The invention relates in general to a capacitor-coupling device, and more particularly to a capacitor-coupling accelerator for use in an integrated circuit.
2. Description of the Related Art
In modem integrated circuit design, the delays of interconnect lines in a chip determine the performance of the whole chip. For the progress of the VLSI manufacturing process and the need for system-on-chip (SOC) integration, the gate delays in a chip are reduced when the devices in the chip are scaled down. Unfortunately, interconnect lines are lengthened along with the chip when the chip becomes larger. Besides, interconnect delays are made larger because greater RC effects result from the smaller line width of the interconnect lines and the narrower space between the interconnect lines. The performance of the whole chip would thus be degraded. As a result, the reduction in the interconnect delay is desired to be achieved.
The delay of an interconnect line can be reduced by inserting a buffer into the middle of the interconnect line because the delay time is proportional to the square of the interconnect length, as indicated by the relationship: t∝rcl2. This approach to reduction of the interconnect delay is illustrated in FIG. 1, wherein a buffer is inserted in the middle of the interconnect line. Suppose that the whole interconnect line has a delay time τ2 mm when its length is 2 mm originally. The delay time becomes 2×τ1 mm+τbuffer when the buffer is inserted into the middle of the interconnect line, where τ1 mm is the interconnect delay for one segment of the interconnect line with a length of 1 mm and τbuffer is the delay of the buffer. The delay time may thus reduced if τ2 mm>2×τ1 mm+τbuffer. This approach is commonly used in the industry. The details for the approach is discussed in the literature by Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, and Juho Kim, entitled “Interleaving buffer insertion and transistor sizing into a single optimization”, IEEE Transactions on VLSI systems, vol. 6, no. 4, pp. 625-63, December 1998.
The interconnect delay can also be minimized by using a reduced voltage signal (V), as indicated by the equation t=CV/I deduced from Q=CV=It. This approach is disclosed in the literature by H. Zhang, V. Gerorge and J. M. Rabaey, entitled “Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness”, IEEE Transactions on VLSI Systems, vol. 8, no. 3, pp. 264-272, June, 2000. The delay is reduced in this approach by first reducing the amplitude of a signal to be transferred at the sending end and then amplifying the received signal at the receiving end to make this signal have the original amplitude at the sending end. This approach requires a number of control signals or power supplies, thus resulting in difficulties in implementation. Thus, the approach is not suitable for mass production.
In addition, the transient sensitivity of the resistive interconnect signals can be accelerated by controlling the output stage according to a fast control signal and a slow control signal that are produced by a Schmitt trigger and a transient sensitive trigger (TST). This approach is disclosed by Tmofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, and Masakazu Yamashina in the literature entitled “Capacitor coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 531-536, April 1996. Unfortunately, this approach has a disadvantage that the speed of discharging and charging processes involved in the output stage is reduced because the loops for discharging and charging are in serial connection with two PMOS and NMOS, respectively. The accelerating effect is thus restricted.
As discussed above, the conventional approaches to the reduction of the interconnect delay are difficult to control and have limited performance. Hence, it is desirable to provide an accelerating circuit that is of high performance and readily to be controlled so as to achieve the reduction in interconnect delay as well as to enhance the overall performance of the chip.